View LTC1297BCN8_5079771.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc1292/ltc1297 single chip 12-bit data acquisition systems s f ea t u re d u escriptio key specificatio s u u a o pp l ic at i ty p i ca l n resolution: 12 bits n fast conversion time: 12 m s max over temp n low supply current: 6.0ma n shutdown supply current: 5 m a (ltc1297) n built-in sample-and-hold n single supply 5v operation n 60khz maximum throughput rate (ltc1292) n power shutdown after each conversion (ltc1297) n direct 3-wire interface to most mpu serial ports and all mpu parallel ports n analog inputs common mode to supply rails the ltc1292/ltc1297 are data acquisition systems that contain a 12-bit, switched-capacitor successive approxi- mation a/d, a differential input, sample-and-hold on the (+) input, and serial i/o. when the ltc1297 is idle between conversions it automatically powers down reducing the supply current to 5 m a, typically. the ltc1292 is capable of digitizing signals at a 60khz rate and with the devices excellent ac characteristics, it can be used for dsp appli- cations. all these features are packaged in an 8-pin dip and are made possible using ltcmos tm switched-capaci- tor technology. the serial i/o is designed to communicate without external hardware to most mpu serial ports and all mpu parallel i/o ports allowing data to be transmitted over three wires. because of their accuracy, ease of use and small package size these devices are well suited for digitizing analog signals in remote applications where minimum number of interconnects and power consumption are important. ltcmos is trademark of linear technology corporation 12-bit differential input data acquisition system + differential inputs common mode range 0v to 5v * 1n4148 v ref d out clk v cc ltc1297 +in gnd cs ?n lt1027 4.7? tantalum + 8v to 40v 1? 22? tantalum do mc68hc11 sck miso *for overvoltage protection limit the input current to 15ma per pin or clamp the inputs to v cc and gnd with 1n4148 diodes. conversion results are not valid when any input is overvoltaged (v in < gnd or v in > v cc ). see section on overvoltage protection in the applications information. ltc1292/7 ta01 + 5v f sample (hz) 10 average i cc ( m a) 100 1000 10000 1 100 10k ltc1297?ta02 1 10 1k 100k power supply current vs sampling frequency
2 ltc1292/ltc1297 wu u package / o rder i for atio a u g w a w u w a r b s o lu t exi t i s (notes 1 and 2) supply voltage (v cc ) to gnd .................................. 12v voltage analog and reference inputs..................................... C0.3v to v cc + 0.3v digital inputs ........................................ C0.3v to 12v digital outputs .......................... C0.3v to v cc + 0.3v power dissipation .............................................. 500mw operating temperature range ltc1292/ltc1297bc, ltc1292/ltc1297cc, ltc1292/ltc1297dc ............................ 0 c to 70 c ltc1292/ltc1297bi, ltc1292/ltc1297ci, ltc1292/ltc1297di ........................ C40 c to 85 c storage temperature range ................ C65 c to 150 c lead temperature (soldering, 10 sec.)................ 300 c order part number t jmax = 150 c, q ja =100 c/w (j8) t jmax = 100 c, q ja =130 c/w (n8) co verter a d ultiplexer characteristics uu w (note 3) 1 2 3 4 top view n8 package 8-lead plastic dip cs +in in gnd j8 package 8-lead ceramic dip 8 7 6 5 v cc clk d out v ref parameter conditions min typ max min typ max min typ max units offset error (note 4) l 3.0 3.0 3.0 lsb linearity error (inl) (note 4 & 5) l 0.5 0.5 0.75 lsb gain error (note 4) l 0.5 1.0 4.0 lsb minimum resolution for which no 12 12 12 bits missing codes are guaranteed analog and ref input range (note 7) l C0.05v to v cc + 0.05v v on channel leakage current on channel = 5v l 1 1 1 m a (note 8) off channel = 0v on channel = 0v l 1 1 1 m a off channel = 5v off channel lekage current on channel = 5v l 1 1 1 m a (note 8) off channel = 0v on channel = 0v l 1 1 1 m a off channel = 5v ltc1292c ltc1297c ltc1292b ltc1297b ltc1292d ltc1297d ltc1292bin8 ltc1297bin8 ltc1292cin8 ltc1297cin8 ltc1292din8 ltc1297din8 ltc1292bcj8 ltc1297bcj8 ltc1292ccj8 ltc1297ccj8 ltc1292dcj8 ltc1297dcj8 ltc1292bcn8 LTC1297BCN8 ltc1292ccn8 ltc1297ccn8 ltc1292dcn8 ltc1297dcn8 for military temperature ranges please contact factory.
3 ltc1292/ltc1297 ac characteristics (note 3) ltc1292b/ltc1297b ltc1292c/ltc1297c ltc1292d/ltc1297d (note 3) symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v l 2.0 v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C2.5 m a v oh high level output voltage v cc = 4.75v, i o = C10 m a 4.7 v i o = 360 m a l 2.4 4.0 v v ol low level output voltage v cc = 4.75v, i o = 1.6ma l 0.4 v i oz high z output leakage v out = v cc , cs high l 3 m a v out = 0v, cs high l C3 m a i source output source current v out = 0v C20 ma i sink output sink current v out = v cc 20 ma ltc1292b/ltc1297b ltc1292c/ltc1297c ltc1292d/ltc1297d digital a d dc electrical characteristics u symbol parameter conditions min typ max units f clk clock frequency v cc = 5v (note 6) (note 9) 1.0 mhz t smpl analog input sample time see operating sequence ltc1292 1.5clk ltc1297 0.5clk+5.5 m s t conv conversion time see operating sequence 12 clk cycles t cyc total cycle time see operating sequence (note 6) ltc1292 14clk+2.5 m s ltc1297 14clk+6 m s t ddo delay time, clk to d out data valid see test circuits l 160 300 ns t dis delay time, cs - to d out hi-z see test circuits l 80 150 ns t en delay time, clk to d out enabled see test circuits l 80 200 ns t hdo time output data remains valid after clk 130 ns t f d out fall time see test circuits l 65 130 ns t r d out rise time see test circuits l 25 50 ns t whclk clk high time v cc = 5v (note 6) 300 ns t wlclk clk low time v cc = 5v (note 6) 400 ns t sucs setup time, cs before clk - v cc = 5v (note 6) ltc1292 50 ns (ltc1297 wakeup time) ltc1297 5.5 m s t whcs cs high time between data transfer cycles v cc = 5v (note 6) ltc1292 2.5 m s ltc1297 0.5 m s t wlcs cs low time during data transfer v cc = 5v (note 6) ltc1292 14clk ltc1297 14clk+ 5.5 m s c in input capacitance analog inputs on channel 100 pf analog inputs off channel 5 pf digital inputs 5 pf
4 ltc1292/ltc1297 digital a d dc electrical characteristics u (note 3) symbol parameter conditions min typ max units i cc positive supply current cs high ltc1292 l 612 ma cs low ltc1297 l 612 ma ltc1297bc, ltc1297cc, ltc1297dc l 510 m a ltc1297bi, ltc1297ci, ltc1297di l 515 m a ltc1297bm, ltc1297cm, ltc1297dm i ref reference current cs high l 10 50 m a ltc1292b/ltc1297b ltc1292c/ltc1297c ltc1292d/ltc1297d cc hara terist ics uw a t y p i ca lper f o r c e cs high power shutdown clk off ambient temperature (?) ?0 supply current (ma) 7 8 9 30 70 ltc1292/7 g02 6 5 30 ?0 50 90 110 4 3 10 10 130 clk = 1mhz v cc = 5v supply voltage (v) 4 supply current (ma) 4 6 6 ltc1292/7 g01 2 0 5 10 8 clk = 1mhz t a = 25? ltc1297 supply current (power shutdown) vs temperature ambient temperature (?) ?0 0 supply current ( m a) 1 3 4 5 10 7 0 50 75 ltc1292/7 g03 2 8 9 6 ?5 25 100 125 v cc = 5v v ref = 5v cs high clk off supply current vs temperature supply current vs supply voltage below gnd or one diode drop above v cc . be careful during testing at low v cc levels (4.5v), as high level reference or analog inputs (5v) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full scale. this spec allows 50mv forward bias of either diode. this means that as long as the reference or analog input does not exceed the supply voltage by more than 50mv, the output code will be correct. to achieve an absolute 0v to 5v input voltage range will therefore require a minimum supply voltage of 4.950v over initial tolerance, temperature variations and loading. note 8: channel leakage current is measured after the channel selection. note 9: increased leakage currents at elevated temperatures cause the s/ h to droop, therefore it is recommended that f clk 3 125khz at 125 c, f clk 3 31khz at 85 c, and f clk 3 3khz at 25 c. the l denotes specifications which apply over the operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground (unless otherwise noted). note 3: v cc = 5v, v ref = 5v, clk = 1.0mhz unless otherwise specified. note 4: one lsb is equal to v ref divided by 4096. for example, when v ref = 5v, 1lsb = 5v/4096 = 1.22mv. note 5: linearity error is specified between the actual end points of the a/d transfer curve. the deviation is measured from the center of the quantization band. note 6: recommended operating conditions. note 7: two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop
5 ltc1292/ltc1297 cc hara terist ics uw a t y p i ca lper f o r c e ltc1297 supply current (power shutdown) vs clk frequency reference voltage (v) 0 linearity (lsb = 1/4096 v ref ) 0.75 1.00 1.25 4 ltc1292/7 g06 0.50 0.25 0 1 2 3 5 v cc = 5v change in gain vs temperature * as the clk frequency is decreased from 1mhz, minimum clk frequency ( d error 0.1lsb) represents the frequency at which a 0.1lsb shift in any code transition from its 1mhz value is first detected (note 9). clk frequency (khz) 0 supply current ( m a) 15 20 25 800 ltc1292/7 g04 10 5 0 200 400 600 1000 v cc = 5v v ref = 5v cs high cmos logic levels change in linearity vs reference voltage unadjusted offset voltage vs reference voltage reference voltage (v) 1 0.5 0.6 5 ltc1292/7 g05 0.4 0.3 0.1 2 3 4 0.2 0.9 0.8 offset (lsb = 1/4096 v ref ) 0.7 v os = 0.125mv v cc = 5v v os = 0.250mv change in gain vs reference voltage change in offset vs temperature ambient temperature (?) ?0 magnitude of offset change (lsb) 0.3 0.4 0.5 50 ltc1292/7 g08 0.2 0.1 0 ?5 0 25 75 125 100 v cc = 5v v ref = 5v clk = 1mhz change in linearity vs temperature ambient temperature (?) ?0 magnitude of linearity change (lsb) 0.3 0.4 0.5 50 ltc1292/7 g09 0.2 0.1 0 ?5 0 25 75 125 100 v cc = 5v v ref = 5v clk = 1mhz d out delay time vs temperature reference voltage (v) 0 ?.2 change in gain (lsb = 1/4096 v ref ) ?.0 0.8 0.6 0.4 0.2 0 1234 ltc1292/7 g07 5 v cc = 5v ambient temperature (?) ?0 magnitude of gain change (lsb) 0.3 0.4 0.5 50 ltc1292/7 g10 0.2 0.1 0 ?5 0 25 75 125 100 v cc = 5v v ref = 5v clk = 1mhz ambient temperature (?) ?0 minimum clk frequency (mhz) 0.15 0.20 0.25 50 ltc1292/7 g11 0.10 0.05 ?5 0 25 75 125 100 v cc = 5v minimum clock rate for 0.1 lsb error* ambient temperature (?) ?0 d out delay time from clk (ns) 150 200 250 50 ltc1292/7 g12 100 0 ?5 0 25 75 125 100 v cc = 5v 50 msb first data lsb first data
6 ltc1292/ltc1297 cc hara terist ics uw a t y p i ca lper f o r c e 100 0.2 maximum clk frequency* (mhz) 0.4 0.6 0.8 1.0 1k 10k 100k ltc1292/7g13 0 v cc = 5v v ref = 5v clk = 1mhz r source ?( w ) + +in ?n +v in r source maximum filter resistor vs cycle time pi fu ctio s u uu # pin function description 1 cs chip select input a logic low on this input enables the ltc1292/ltc1297. power shutdown is activated on the ltc1297 when cs is brought high. 2, 3 +in, Cin analog inputs these inputs must be free of noise with respect to gnd. 4 gnd analog ground gnd should be tied directly to an analog ground plane. 5v ref reference input the reference input defines the span of the a/d converter and must be kept free of noise with respect to gnd. 6d out digital data output the a/d conversion result is shifted out of this output. 7 clk shift clock this clock synchronizes the serial data transfer. 8v cc positive supply this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. * maximum clk frequency represents the clk frequency at which a 0.1lsb shift in the error at any code transition from its 1mhz value is first detected. ** maximum r filter represents the filter resistor value at which a 0.1lsb change in full scale error from its value at r filter = 0 w is first detected. cycle time (?) 10 maximum r filter ** ( w ) 100 1k 10k 10 1k 10k ltc1292/7 g14 1 100 + +v in c filter 3 1? r filter maximum clock rate vs source resistance r source + ( w ) 100 1 s & h aquisition time to 0.02% (?) 10 100 1000 10000 ltc1292/7 g15 + +v in r source v ref = 5v v cc = 5v t a = 25? 0v to 5v input step sample-and-hold acquisition time vs source resistance input channel leakage current vs temperature ambient temperature (?) ?0 0 input channel leakage current (na) 100 300 400 500 1000 700 ?0 30 50 130 ltc1292/7 g16 200 800 900 600 ?0 10 70 90 110 on channel off channel guaranteed noise error vs reference voltage reference voltage (v) 0 0 peak-to-peak noise error (lsb) 0.25 0.75 1.00 1.25 2 4 5 2.25 0.50 13 1.50 1.75 2.00 ltc1292/7 g17 ltc1292/ltc1297 noise = 200? p-p
7 ltc1292/ltc1297 load circuit for t dis and t en load circuit for t ddo , t r and t f on and off channel leakage current voltage waveforms for d out delay time, t ddo w i dagra b l o c k test circuits voltage waveforms for d out rise and fall times, t r , t f voltage waveforms for t dis input shift register comp sample and hold 12-bit capacitive dac output shift register 12-bit sar control and timing v cc 8 analog input mux 2 3 v ref 5 gnd 4 ?n +in d out 6 1 clk 7 cs ltc1292/7 bd d out 1.4v 3k w 100pf test point ltc1292/7 tc03 d out 3k 100pf test point 5v t dis waveform 2, t en t dis waveform 1 ltc1292/7 tc02 5v a a i off i on polarity off channel on channel ltc1292/7 tc01 clk d out 0.8v t ddo 0.4v 2.4v ltc1292/7 tc04 d out 0.4v 2.4v t r t f ltc1292/7 tc05 d out waveform 1 (see note 1) 2.0v t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. ltc1292/7 tc06
8 ltc1292/ltc1297 test circuits voltage waveforms for t en the ltc1292/ltc1297 are data acquisition components which contain the following functional blocks: 1. 12-bit succesive approximation capacitive a/d converter 2. differential input 3. sample-and-hold (s/h) 4. synchronous, half-duplex serial interface 5. control and timing logic digital considerations serial interface the ltc1292/ltc1297 communicate with microproces- sors and other external circuitry via a synchronous, half- duplex, three-wire serial interface (see operating se- quence). the clock (clk) synchronizes the data transfer with each bit being transmitted on the falling clk edge. the ltc1292/ltc1297 do not require a configuration input word and have no d in pin. they are permanently configured to have a single differential input and to per- form a unipolar conversion. a falling cs initiates data transfer. to allow the ltc1297 to recover from the power shutdown mode, t sucs has to be met. then the first clk pulse enables d out . after one null bit, the a/d conversion result is output on the d out line with a msb-first sequence followed by a lsb-first sequence. with the half-duplex serial interface the d out data is from the current conver- sion. this provides easy interface to msb-first or lsb-first u s a o pp l ic at i wu u i for atio serial ports. bringing cs high resets the ltc1292/ltc1297 for the next data exchange and puts the ltc1297 into its power shutdown mode. table 1. microprocessor with hardware serial interfaces compatible with the ltc1292/ltc1297** d out 0.8v t en b11 cs clk ltc1292/7 tc07 part number type of interface motorola mc6805s2, s3 spi mc68hc11 spi mc68hc05 spi rca cdp68hc05 spi hitachi hd6305 sci synchronous hd6301 sci synchronous hd63701 sci synchronous hd6303 sci synchronous hd64180 sci synchronous national semiconductor cop400 family microwire ? cop800 family mcrowire/plus ? ns8050u microwire/plus hpc16000 family microwire/plus texas instruments tms7002 serial port tms7042 serial port tms70c02 serial port tms70c42 serial port tms32011* serial port tms32020* serial port tms370c050 spi * requires external hardware ** contact factory for interface information for processors not on this list ? microwire and microwire/plus are trademarks of national semiconductor corp.
9 ltc1292/ltc1297 ltc1292 operating sequence u s a o pp l ic at i wu u i for atio motorola spi (mc68hc11) the mc68hc11 has been chosen as an example of an mpu with a dedicated serial port. this mpu transfers data msb first and in 8-bit increments. a dummy d in word sent to the data register starts the spi process. with two 8-bit transfers, the a/d result is read into the mpu (figure 1). for the ltc1292 the first 8-bit transfer clocks b11 through b8 of the a/d conversion result into the processor. the second 8-bit transfer clocks the remaining bits b7 through b0 into microprocessor interfaces the ltc1292/ltc1297 can interface directly (without external hardware) to most popular microprocessors (mpu) synchronous serial formats (see table 1). if an mpu without a dedicated serial port is used, then three of the mpus parallel port lines can be programmed to form the serial link to the ltc1292/ltc1297. included here are one serial interface example and one example showing a parallel port programmed to form the serial interface. figure 1. data exchange between ltc1292 and mc68hc11 clk t cyc cs b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 t conv d out hi-z t smpl t smpl ltc1292/7 ai01 ltc1297 operating sequence clk cs d out mpu received word ltc1292/7 f01 b7 b6 b5 b4 b3 b2 b1 b0 b1 b8 b9 b10 b11 byte 2 b10 b9 b8 b11 o ? ? ? 1st transfer 2nd transfer byte 1 b2 b1 b0 b3 b4 b6 b7 b5 clk t cyc cs b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 t conv d out hi-z t smpl ltc1292/7 ai02 t sucs power shutdown mode
10 ltc1292/ltc1297 the mpu. the data is right-justified in the two memory locations (figure 2). this was made possible by delaying the falling edge of cs till after the second clk. anding the first byte with 0f hex clears the four most significant bits. this operation was not included in the code. it can be inserted in the data gathering loop or outside the loop when the data is processed. u s a o pp l ic at i wu u i for atio label mnemonic operand comments ldaa #$50 configuration data for spcr staa $1028 load data into spcr ($1028) ldaa #$1b config. data for port d ddr staa $1009 load data into port d ddr ldaa #$00 load dummy din word into acc a staa $50 load dummy din data into $50 loop ldx #$1000 load index register x with $1000 ldab #$00 load acc b with $00 ldaa $50 load dummy din into acc a from $50 staa $102a load dummy din into spi, start sck nop delay cs fall time to right justify data mc68hc11 code for ltc1292 interface stab $08, x d0 goes low (cs goes low) nop 6 nops for timing ldaa $1029 check spi status reg ldaa $102a load ltc1292 msbs into acc a staa $61 store msbs in $61 staa $102a load dummy din into spi, start sck nops 6 nops for timing bset $08,x,$01 d0 goes high (cs goes high) ldaa $1029 check spi status register ldaa $102a load ltc1292 lsbs in acc staa $62 store lsbs in $62 jmp loop start next conversion label mnemonic operand comments byte 2 b3 b7 b6 b5 b4 b2 b0 b1 b10 b9 b8 b11 o o oo byte 1 d out from ltc1292 stored on mc68hc11 ram location #61 location #62 msb ltc1292/7 f02 clk d out ltc1292 cs analog inputs do sck miso mc68hc11 figure 2. hardware and software interface to motorola mc68hc11 microcontroller figure 3. data exchange between ltc1297 and mc68hc11 for the ltc1297 (figure 3) a delay must be introduced to accommodate the setup time, t sucs , before the dummy d in word is sent to the data register. the first 8-bit transfer clocks b11 through b6 of the a/d conversion result into the processor. the second 8-bit transfer clocks the re- maining bits b5 through b0 into the mpu. note b1 and b2 from the lsb-first data word have also been clocked in. clk cs d out mpu received word ltc1292/7 f03 b7 b6 b5 b4 b3 b2 b1 b0 b1 b8 b9 b10 b11 byte 2 b8 b7 b6 b9 b10 0 ? b11 1st transfer 2nd transfer byte 1 b0 b1 b2 b1 b2 b4 b5 b3 b2 b3
11 ltc1292/ltc1297 on two port lines and the d out signal is read on a third port line. after a falling clk edge each data bit is loaded into the carry bit and then rotated into the accumulator. once the first 8 msbs have been shifted into the accumulator they are loaded into register r2. the last four bits are shifted in the same way and loaded into register r3. the output data is left-justified in registers r2 and r3 (figure 5). for the ltc1297 four nops need to be inserted in the 8051 code after cs goes low to allow the ltc1297 to wake up from power shutdown (t sucs ). u s a o pp l ic at i wu u i for atio label mnemonic operand comments ldaa #$50 configuration data for spcr staa $1028 load data into spcr ($1028) ldaa #$1b config. data for port d ddr staa $1009 load data into port d ddr ldaa #$00 load dummy din word into acc a staa $50 load dummy din data into $0 loop ldx #$1000 load index register x with $1000 ldab #$00 load acc b with $00 ldaa $50 load din into acc from $50 bclr $08,x,$01 d0 goes low (cs goes low) nop 3 nop for t sucs timing nop nop staa $102a load dummy din into spi, start clk label mnemonic operand comments mc68hc11 code for ltc1297 interface loop1 ldaa $1029 check spi status reg bpl loop1 check if transfer is done ldaa $102a load ltc1297 msbs into acc a staa $61 store msbs in $61 staa $102a load dummy din into spi, start sck loop2 ldaa $1029 check spi status res bpl loop2 check if transfer is done bset $08x,$01 d0 goes high (cs goes high) ldaa $102a load ltc1297 lsbs into acc a staa $62 store lsbs in $62 ror $61 rotate right with carry ror $62 needed to right justify ror $61 the data in $61 and $62 ror $62 jmp loop start next conversion byte 2 b3 b7 b6 b5 b4 b2 b0 b1 b10 b9 b8 b11 o o oo byte 1 d out from ltc1297 stored on mc68hc11 ram location #61 location #62 msb ltc1292/7 f04 clk d out ltc1297 cs analog inputs do sck miso mc68hc11 figure 4. hardware and software interface to motorola mc68hc11 microcontroller the data is right- justified in the two memory locations by rotating right twice (figure 4). anding the first byte with 0f hex clears the four most significant bits. this operation was not included in the code. it can be inserted in the data gathering loop or outside the loop when the data is processed. interfacing to the parallel port of the intel 8051 family the intel 8051 has been chosen to show the interface between the ltc1292/ltc1297 and parallel port microprocessors. the signals cs and clk are generated
12 ltc1292/ltc1297 u s a o pp l ic at i wu u i for atio figure 5. hardware and software interface to intel 8051 processor label mnemonic operand comments mov p1,#02h bit 1 port 1 set as input clr p1.3 clk goes low setb p1.4 cs goes high cont clr p1.4 cs goes lo nop 4 nop for ltc1297 t sucs (wakeup nop time) (not needed for ltc1292) nop nop setb p1.3 clk goes high clr p1.3 clk goes low setb p1.3 clk goes high clr p1.3 clk goes low mov r4,#08h load counter loop mov c,p1.1 read data bit into carry rlc a rotate data bit into acc setb p1.3 clk goes high clr p1.3 clk goes low djnz r4,loop next bit mov r2,a store msbs in r2 mov c,p1.1 read data bit into carry clr a clear acc rlc a rotate data bit (b3) into acc setb p1.3 clk goes high clr p1.3 clk goes low mov c,p1.1 read data bit into carry rlc a rotate data bit (b2) into acc setb p1.3 clk goes high clr p1.3 clk goes low mov c,p1.1 read data bit into carry rlc a rotate data bit (b1) into acc setb p1.3 clk goes high clr p1.3 clk goes low mov c,p1.1 read data bit into carry setb p1.4 cs goes high rrc a rotate data bit (b0) into acc rrc a rotate right into acc rrc a rotate right into acc rrc a rotate right into acc mov r3,a store lsbs in r3 ajmp cont start next conversion label mnemonic operand comments 8051 code sharing the serial interface the ltc1292/ltc1297 can share the same two-wire serial interface with other peripheral components or other ltc1292/ltc1297s (figure 6). in this case, the cs signals decide which ltc1292 is being addressed by the mpu. analog considerations grounding the ltc1292/ltc1297 should be used with an analog ground plane and single point grounding techniques. do not use wire wrapping techniques to breadboard and evaluate the device. to achieve the optimum performance d out from ltc1292/ltc1297 stored in 8051 ram b3 b2 b0 b1 o o oo r3 b7 b6 b5 b4 b10 b9 b8 b11 r2 msb analog inputs clk d out ltc1292 ltc1297 cs p1.4 p1.3 p1.1 8051 ltc1292/7 f05 cs d out b11 b7 b8 b9 b10 b4 b5 b6 b3 b2 b1 b0 clk
13 ltc1292/ltc1297 u s a o pp l ic at i wu u i for atio figure 6. several ltc1292/ltc1297s sharing one 2-wire serial interface ltc1292 ltc1297 2 channels 2 channels 2 channels cs cs cs 2 2 2 2 2-wire serial interface to other peripherals or ltc1292/ltc1297s 2 10 output port serial data mpu ltc1292 ltc1297 ltc1292 ltc1297 ltc1292/7 f06 figure 7. example ground plane for the ltc1292/ltc1297 1 2 3 4 5 6 7 8 22? tantalum v cc ltc1292/7 f07 ltc1292 ltc1297 0.1? cs v cc horizontal: 10 m s/div minimum and the v cc supply should have a low output impedance such as obtained from a voltage regulator (e.g., lt323a). for high frequency bypassing a 0.1 m f ceramic disk placed in parallel with the 22 m f is recommended. again the leads should be kept to a minimum. figures 8 and 9 show the effects of good and poor v cc bypassing. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1292/ ltc1297 have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem. if large source resistances are used or if slow settling op amps drive the inputs, take care to insure that the transients caused by the current spikes settle completely before the conversion begins. use a pc board. the ground pin (pin 4) should be tied directly to the ground plane with minimum lead length (a low profile socket is fine). figure 7 shows an example of an ideal ltc1292/ltc1297 ground plane design for a two- sided board. of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. bypassing for good performance, v cc must be free of noise and ripple. any changes in the v cc voltage with respect to ground during a conversion cycle can induce errors or noise in the output code. v cc noise and ripple can be kept below 0.5mv by bypassing the v cc pin directly to the analog ground plane with a minimum of 22 m f tantalum capacitor and with leads as short as possible. the lead from the device to the v cc supply also should be kept to a horizontal: 10 m s/div figure 8. poor v cc bypassing. noise and ripple can cause a/d errors figure 9. good v cc bypassing keeps noise and ripple on v cc below 1mv vertical: 0.5mv/div vertical: 0.5mv/div
14 ltc1292/ltc1297 u s a o pp l ic at i wu u i for atio source resistance the analog inputs of the ltc1292/ltc1297 look like a 100pf capacitor (c in ) in series with a 500 w resistor (r on ) (figures 10a and 10b). c in gets switched between (+) and (C) inputs once during each conversion cycle. large external source resistors and capacitances will slow the settling of the inputs. it is important that the overall rc time constant is short enough to allow the analog inputs to settle completely within the allowed time. + input settling the input capacitor for the ltc1292 is switched onto the + input during the sample phase (t smpl , see figures 11a, 11b and 11c). the sample period can be as short as t whcs + 1/2 clk cycle or as long as t whcs + 1 1/2 clk cycles before a conversion starts. this variability depends on where cs falls relative to clk. the voltage on the + input must settle completely within the sample period. minimizing r source + and c1 will improve the settling time. if large + input source resistance must be used, the sample time can be increased by using a slower clk frequency. with the minimum possible sample time of 3.0 m s, r source + < 2.0k and c1 < 20pf will provide adequate settling time. the sample period for the ltc1297 starts on the falling edge of cs and ends on the falling edge of the first clk figure 11a. setup time (t sucs ) is met for the ltc1292 + and C input settling windows (figure 12). the length of the sample period is t sucs +0.5 clk cycles. again, the voltage on the + input must settle completely within the sample period. if large + input source resistance must be used, the sample time can be increased by using a slower clk frequency or by increasing figure 10a. analog input equivalent circuit for the ltc1292 figure 10b. analog input equivalent circuit for the ltc1297 cs - r on 500 w t whcs + 0.5 clk c in 100pf ltc1292 ?? input r source + v in + c1 ? input r source v in ? c2 ltc1292/7 f10a cs r on 500 w t sucs + 0.5 clk c in 100pf ltc1297 ?? input r source + v in + c1 ? input r source v in ? c2 ltc1292/7 f10b d out clk b11 hi-z b9 b10 ltc1292/7 f11a cs 1st bit test (? input must settle during this time t sucs t whcs t smpl (+) input must settle during this time (+) input (? input
15 ltc1292/ltc1297 u s a o pp l ic at i wu u i for atio figure 11b. setup time (t sucs ) is met for the ltc1292 figure 11c. setup time (t sucs ) is not met for the ltc1292 t sucs . with the minimum possible sample time of 6 m s, r source + < 5k and c1 < 20pf will provide adequate settling time . in general for both the ltc1292 and ltc1297 keep the product of the total resistance and the total capacitance less than t smpl / 9. if this condition can not be met, then make c1 > 0.47 m f (see rc input filtering section). C input settling at the end of the sample phase the input capacitor switches to the C input and the conversion starts (see figures 11a, 11b, 11c and 12). during the conversion, the + input voltage is effectively held by the sample-and-hold and will not affect the conversion result. it is critical that the d out clk b11 hi-z b9 b10 ltc1292/7 f11b cs 1st bit test (? input must settle during this time t whcs t smpl (+) input must settle during this time (+) input (? input d out clk b11 hi-z b10 ltc1292/7 f11c cs 1st bit test (? input must settle during this time t whcs t smpl (+) input must settle during this time (+) input (? input
16 ltc1292/ltc1297 figure 12. + and C input settling windows for the ltc1297 C input voltage be free of noise and settle completely during the first clk cycle of the conversion. minimizing r source C and c2 will improve settling time. if large C input source resistance must be used the time can be extended by using a slower clk frequency. at the maximum clk frequency of 1mhz, r source C < 250 w and c2 < 20pf will provide adequate settling. input op amps when driving the analog inputs with an op amp it is important that the op amp settles within the allowed time (see figures 11a, 11b, 11c and 12). again the + and C input sampling times can be extended as described above to accommodate slower op amps. most op amps including the lt1006 and lt1013 single supply op amps can be made to settle well even with the minimum settling windows of 3.0 m s for the ltc1292 or 6.0 m s for the ltc1297 (+ input) and 1 m s (C input) that occurs at the maximum clock rate of 1mhz. figures 13 and 14 show examples of both adequate and poor op amp settling. vertical: 5mv/div horizontal: 500ns/div horizontal: 20 m s/div figure 13. adequate settling of op amp driving analog input vertical: 5mv/div figure 14. poor op amp settling can cause a/d errors u s a o pp l ic at i wu u i for atio d out clk b11 hi-z b10 ltc1292/7 f12 cs 1st bit test (? input must settle during this time t whcs t smpl (+) input must settle during this time (+) input (? input t sucs
17 ltc1292/ltc1297 rc input filtering it is possible to filter the inputs with an rc network as shown in figure 15. for large values of c f (e.g., 1 m f) the capacitive input switching currents are averaged into a net dc current. a filter should be chosen with a small resistor and large capacitor to prevent dc drops across the resistor. the magnitude of the dc current is approximately i dc = 100pf v in /t cyc and is roughly proportional to v in . when running the ltc1292(ltc1297) at the minimum cycle time of 16.5 m s (20 m s), the input current equals 30 m a (25 m a) at v in = 5v. here a filter resistor of 4 w (5 w ) will cause 0.1lsb of full scale error. if a large filter resistor must be used, errors can be reduced by increasing the cycle time as shown in the typical performance characteristics curve maximum filter resistor vs cycle time. figure 15. rc input filtering curve of s&h acquisition time vs source resistance). the input voltage is sampled during the t smpl time as shown in figure 11. the sampling interval begins at the rising edge of cs for the ltc1292, and at the falling edge of cs for the ltc1297, and continues until the falling edge of the clk before the conversion begins. on this falling edge the s&h goes into the hold mode and the conversion begins. differential input with a differential input the a/d no longer converts a single voltage but converts the difference between two voltages. the voltage on the +in pin is sampled and held and can be rapidly time-varying as in single-ended mode. the voltage on the Cin pin must remain constant and be free of noise and ripple throughout the conversion time. otherwise the differencing operation will not be done accurately. the conversion time is 12 clk cycles. therefore a change in the Cin input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the Cin input this error would be: vfv f error max in peak clk ( ) ( ) = () ? ? ? ? 2 12 p where f (Cin) is the frequency of the Cin input voltage, v peak is its peak amplitude and f clk is the frequency of the clk. usually v error will not be significant. for a 60hz signal on the Cin input to generate a 0.25lsb error (300 m v) with the converter running at clk = 1mhz, its peak value would have to be 66mv. rearranging the above equation the maximum sinusoidal signal that can be digitized to a given accuracy is given as: f v v f in max error max peak clk ( ) () = p ? ? ? ? ? ? ? ? 2 12 for 0.25lsb error (300 m v) the maximum input sinusoid with a 5v peak amplitude that can be digitized is 0.8hz. reference input the voltage on the reference input of the ltc1292/ ltc1297 determine the voltage span of the a/d con- verter. the reference input has transient capacitive switching currents due to the switched-capacitor con- input leakage current input leakage currents also can create errors if the source resistance gets too large. for example, the maximum input leakage specification of 1 m a (at 125 c) flowing through a source resistance of 1k will cause a voltage drop of 1mv or 0.8lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see typical performance characteristics curve input channel leakage current vs temperature). sample-and-hold single-ended input the ltc1292/ltc1297 provide a built-in sample-and- hold (s&h) function on the +in input for signals acquired in the single-ended mode (Cin pin grounded). the sample- and-hold allows the ltc1292/ltc1297 to convert rapidly varying signals (see typical performance characteristics r filter c filter ltc1292/7 f15 ltc1292 ltc1297 ? i dc v in u s a o pp l ic at i wu u i for atio 1292/7 e1 1292/7 e2
18 ltc1292/ltc1297 u s a o pp l ic at i wu u i for atio figures 17 and 18 show examples of both adequate and poor settling. using a slower clk will allow more time for the reference to settle. even at the maximum clk rate of 1mhz most references and op amps can be made to settle within the 1 m s bit time. for example the lt1027 will settle adequately. with a 10 m f bypass capacitor at v ref the lt1021 can also be used. reduced reference operation the effective resolution of the ltc1292/ltc1297 can be increased by reducing the input span of the con- verter. the ltc1292/ltc1297 exhibit good linearity over a range of reference voltages (see typical perfor- mance characteristics curves of change in linearity vs reference voltage). care must be taken when operat- ing at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. offset and noise are factors that must be considered when operating at low v ref values. the internal reference for v ref has been tied to the gnd pin. any voltage drop from the gnd pin to the ground plane will cause a gain error. offset with reduced v ref the offset of the ltc1292/ltc1297 has a larger effect on the output code when the a/d is operated with a reduced reference voltage. the offset (which is typi- cally a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical performance characteristics curve of unadjusted off- set error vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example a v os of 0.1mv, which is 0.1lsb with a 5v reference becomes 0.4lsb with a 1.25v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offset- ting the Cin input to the ltc1292/ltc1297. noise with reduced v ref the total input referred noise of the ltc1292/ltc1297 can be reduced to approximately 200 m v p-p using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 5v reference input but will version technique (see figure 16). during each bit test of the conversion (every clk cycle) a capacitive current spike will be generated on the reference pin by the a/d. these current spikes settle quickly and do not cause a problem. if slow settling circuitry is used to drive the reference input, take care to insure that transients caused by these current spikes settle completely during each bit test of the conversion. r on 8pf to 40pf ltc1292 ltc1297 ref + r out v ref every clk cycle 14 13 ref ltc1292/7 f16 figure 16. reference input equivalent circuit horizontal: 1 m s/div figure 17. adequate reference settling (lt1027) horizontal: 10 m s/div figure 18. poor reference settling can cause a/d errors vertical: 0.5mv/div vertical: 0.5mv/div
19 ltc1292/ltc1297 become a larger fraction of an lsb as the size of the lsb is reduced. the typical performance characteristics curve of noise error vs reference voltage shows the lsb contribution of this 200 m v of noise. for operation with a 5v reference, the 200 m v noise is only 0.16lsb peak-to-peak. here the ltc1292/ltc1297 noise will contribute virtually no uncertainty to the output code. for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1.25v reference, this 200 m v noise is 0.64lsb peak- to-peak. this will reduce the range of input voltages over which a stable output code can be achieved by 0.64lsb. now, averaging readings may be necessary. this noise data was taken in a very clean test fixture. any setup induced noise (noise or ripple on v cc , v ref or v in ) will add to the internal noise. the lower the reference voltage used, the more critical it becomes to have a noise-free setup. gain error due to reduced v ref the gain error of the ltc1292/ltc1297 is very good over a wide range of reference voltages. the error component that is seen in the typical performance characteristics curve change in gain error vs refer- ence voltage is due to the voltage drop on the gnd pin from the device to the ground plane. to minimize this error the ltc1292/ltc1297 should be soldered di- rectly onto the pc board. the internal reference point for v ref is tied to gnd. any voltage drop in the gnd pin will make the reference voltage, internal to the device, less than what is applied externally (figure 19). this drop is typically 420 m v due to the product of the pin u s a o pp l ic at i wu u i for atio n snr db = ? ? ? ? . . 176 602 this is the effective number of bits (enob). for the example shown in figures 20a and 20b, n = 11.8 bits and 9.9 bits, respectively. figure 21 shows a plot of enob as a function of input frequency. the 2nd har- monic distortion term accounts for the degradation of the enob as f in approaches f s /2. figure 22 shows an fft plot of the output spectrum for two tones applied to the input of the a/d. nonlinearities in the a/d will cause distortion products at the sum and difference frequencies of the fundamentals and prod- ucts of the fundamentals. this is classically referred to as intermodulation distortion (imd). ltc1292 ltc1297 ref+ r pin i cc dac ref v ref gnd ltc1292/7 f19 reference voltage resistance (r pin ) and the ltc1292/ltc1297 supply current. for example, with v ref = 1.25v this will result in a gain error change of C1.0lsb from the gain error measured with v ref = 5v. ltc1292 ac characteristics two commonly used figures of merit for specifying the dynamic performance of the a/ds in digital signal processing applications are the signal-to-noise ratio (snr) and the effective number of bits (enob). snr is the ratio of the rms magnitude of the fundamental to the rms magnitude of all the non-fundamental signals up to the nyquist frequency (half the sampling fre- quency). the theoretical maximum snr for a sine wave input is given by: snr = (6.02n + 1.76db) where n is the number of bits. thus the snr depends on the resolution of the a/d. for an ideal 12-bit a/d the snr is equal to 74db. fast fourier transform (fft) plots of the output spectrum of the ltc1292 are shown in figures 20a and 20b. the input (f in ) frequencies are 1khz and 28khz with the sampling frequency (f s ) at 58.8 khz. the snrs obtained from the plots are 73.0db and 61.5db. by rewriting the snr expression it is possible to obtain the equivalent resolution based on the snr measure- ment. figure 19. parasitic resistance in gnd pin 1292/7 e3
20 ltc1292/ltc1297 u s a o pp l ic at i wu u i for atio figure 20a. f in = 1khz, f s = 58.8khz, snr = 73.0db figure 20b. f in = 28khz, f s = 58.8khz, snr = 61.5db figure 21. ltc1292 enob vs input frequency figure 22. f in1 = 5.1khz, f in2 = 5.6khz, f s = 58.8khz overvoltage protection applying signals to the ltc1292/ltc1297s analog inputs that exceed the positive supply or that go below ground will degrade the accuracy of the a/d and possi- bly damage the devices. for example this condition would occur if a signal is applied to the analog inputs before power is applied to the ltc1292/ltc1297. an- other example is the input source is operating from different supplies of larger value than the ltc1292/ ltc1297. these conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp or current limit the input source. there are two ways to protect the inputs. in figure 23 diode clamps from the inputs to v cc and gnd are used. the second method is to put resistors in series with the analog inputs for current limiting. limit the current to 15ma per channel. the +in input can accept a resistor value of 1k but the Cin input cannot accept more than 250 w when clocked at its maximum clock frequency of 1mhz. if the ltc1292/ltc1297 are clocked at the maximum clock frequency and 250 w is not enough to current limit the input source, then the clamp diodes are recommended (figures 24a and 24b). the reason for the limit on the resistor value is that the msb bit test is affected by the value of the resistor placed at the Cin input (see discussion on analog inputs and the typical performance characteristics maximum clk frequency vs source resistance). frequency (khz) 0 ?0 ?0 ?0 15 25 ltc1292/7 f20a ?0 ?00 510 20 30 ?20 ?40 magnitude (db) 0 frequency (khz) 0 ?0 ?0 ?0 15 25 ltc1292/7 f22 ?0 ?00 510 20 30 ?20 ?40 magnitude (db) 0 frequency (khz) 0 ?0 ?0 ?0 15 25 ltc1292/7 f20b ?0 ?00 510 20 30 ?20 ?40 magnitude (db) 0 frequency (khz) 0 effective number of bits 9.5 10.0 10.5 60 100 lt1292/7 f21 9.0 8.5 8.0 20 40 80 11.0 11.5 12.0 f s = 58.8khz
21 ltc1292/ltc1297 if v cc and v ref are not tied together, then v cc should be turned on first, then v ref . if this sequence cannot be met, connecting a diode from v ref to v cc is recom- mended (see figure 25). because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device v cc without damaging the device. u s a o pp l ic at i wu u i for atio figure 26. quick look circuit for the ltc1292 5v ltc1292/7 f23 1n4148 diodes v cc clk d out v ref cs +in in gnd ltc1292 ltc1297 5v ltc1292/7 f24 1n4148 diodes 1k v cc clk d out v ref cs +in in gnd ltc1292 ltc1297 figure 24b. overvoltage protection with diode clamps and current limiting resistor figure 23. overvoltage protection with clamp diodes 5v ltc1292/7 f25 1n4148 5v v cc clk d out v ref cs +in in gnd ltc1292 ltc1297 figure 25. separate v cc and v ref supplies 5v ltc1292/7 f24a 250 w 1k v cc clk d out v ref cs +in in gnd ltc1292 ltc1297 figure 24a. overvoltage protection with current limiting resistors to oscilloscope cd4520 ltc1292/7 f26 q1 reset v dd en clk q2 q3 q4 0.1? v in f/32 +5v clock in 1mhz 22? clk en q2 q3 q4 v ss q1 reset v cc clk d out v ref cs +in in gnd ltc1292
22 ltc1292/ltc1297 u s a o pp l ic at i wu u i for atio lsb (b0) lsb-first data (b1) msb (b11) null bit vertical: 5v/div horizontal: 2 m s/div clk cs d out a quick look circuit for the ltc1297 a circuit similar to the one used for the ltc1292 can be used for the ltc1297(figure 28). a one shot has been generated with nand gates, a resistor and capacitor to satisfy the setup time t sucs . this can be eliminated if a slower clock is used. when cs goes low the one shot is triggered. this turns off the clock to the ltc1297 for a fixed time to meet t sucs . once the clock starts d out is shifted out one bit at a time. cs is driven at 1/64 the clock rate by the 74hc393. the output data from the d out pin can be viewed on an oscilloscope that is set to trigger on the falling edge of cs. see figure 29. cs clk d out null bit msb (b11) lsb-first data (b1) lsb (b0) vertical: 5v/div horizontal: 5 m s/div figure 29. scope trace of the ltc1297 quick look circuit showing a/d output 101010101010 (aaa hex ) figure 27. scope trace of the ltc1292 quick look circuit showing a/d output 101010101010 (aaa hex ) figure 28. quick look circuit for the ltc1297 to oscilloscope ltc1292/7 f28 0.1? v in f/64 5v 340 w 22? tantalum v cc clk d out v ref cs +in in gnd ltc1297 74hc393 a1 clr1 1qa 1qb 1qc 1qd gnd v cc a2 clr2 2qa 2qb 2qc 2qd + f 0.02 m f clock in 1mhz a quick look circuit for the ltc1292 users can get a quick look at the function and timing of the ltc1292 by using the quick look circuit in figure 26. v ref is tied to v cc . v in is applied to the +in input and the Cin input is tied to the ground plane. cs is driven at 1/32 the clock rate by the cd4520 and d out outputs the data. the output data from the d out pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of cs (figure 27). note the lsb data is partially clocked out before cs goes high.
23 ltc1292/ltc1297 u s a o pp l ic at i wu u i for atio opto-isolated temperature monitor amplification of sensor outputs is often required to generate a signal large enough to be properly digitized. for example, a j-type thermocouple provides only 52 m v/ c. the 5 m v offset of the ltc1050 chopper op amp generates less than 0.1 c error (figure 31). cold junction compensation is provided by the lt1025a. (for more detail see ltc design note 5). in the opto-isolated interface two signals are generated from one. this allows a two-wire interface to the ltc1292. a long high signal (>1ms) on the clk in input allows the 0.1 m f capacitor to discharge taking cs high. this resets the a/d for the next conversion. when clk in starts toggling, cs goes low and stays there until the next extended clk in high time. see figure 30. 5v/div a clk in cs data out 20 m s/div + 1 f type j j r gnd lt1025a v in h 2 2 3 + ltc1050 7 4 6 + m 0.33 f m 178k 0.1% 3.4k 0.1% 2k 0.1% 47 w + 1 f m gnd ltc1292 v cc ?n +in cs clk d out v ref + 4.7 f m 3 w + 0.1 f m 10k 1n4148 8 7 6 5 1 2 3 4 + 22 f m lt1019-2.5 500k 1 2 1k clk in 3 4 500k 3 4 5k data out 1 2 6 1k 4n28s 1n4148 0? ?500? temperature range isolated 5v 4 5 + a 6 100k 74c14 5v 5v 5k ltc1292/7 f31 1n4148 figure 31. opto-isolated temperature monitor figure 30. opto-isolated temperature monitor digital waveforms information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 ltc1292/ltc1297 j8 package 8-lead ceramic dip 0.290 ?0.320 (7.366 ?8.128) 0.008 ?0.018 (0.203 ?0.457) 0??15 0.385 ?0.025 (9.779 ?0.635) 0.005 (0.127) min 0.405 (10.287) max 0.220 ?0.310 (5.588 ?7.874) 12 3 4 87 65 0.025 (0.635) rad typ 0.045 ?0.068 (1.143 ?1.727) full lead option 0.023 ?0.045 (0.584 ?1.143) half lead option corner leads option (4 plcs) j8 0293 0.014 ?0.026 (0.360 ?0.660) 0.200 (5.080) max 0.015 ?0.060 (0.381 ?1.524) 0.125 3.175 min 0.100 ?0.010 (2.540 ?0.254) 0.045 ?0.068 (1.143 ?1.727) note: lead dimensions apply to solder dip or tin plate leads. n8 package 8-lead plastic dip n8 0392 0.045 ?0.015 (1.143 ?0.381) 0.100 ?0.010 (2.540 ?0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 ?0.005 (3.302 ?0.127) 0.020 (0.508) min 0.018 ?0.003 (0.457 ?0.076) 0.125 (3.175) min 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.320 (7.620 ?8.128) 0.325 +0.025 0.015 +0.635 0.381 8.255 () 12 3 4 87 6 5 0.250 ?0.010 (6.350 ?0.254) 0.400 (10.160) max linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 lt/gp 0294 2k rev a ? printed in usa ? linear technology corporation 1994 package descriptio u dimensions in inches (millimeters) unless otherwise noted.

▲Up To Search▲

Price & Availability of LTC1297BCN8

	To Download LTC1297BCN8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .